Inverse Quantizer

ABSTRACT

An inverse quantizing device includes memories which are addressed by input quantized coefficients and quantization levels and store resultant data of inverse quantization in groups such as intra DC, intra AC and non-intra. A control section discriminates the group of an input data to be inverse-quantized according to input block-type and block-strobe signals, selects one of the memories according to the discriminated result, and controls the selected memory to output the resultant data of inverse quantization stored therein. According to the device, real time processing of the input data is achieved with its simplified construction.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an image data compression/expansiontechnique, and more particularly to an inverse quantizing device forinverse-quantizing a compressed image data.

2. Description of the Prior Art

International Standards Organization (ISO) has proposed using the MPEGSM3 model as a data compression standard for an image in motion.

In image data compression, transform coefficients obtained byDCT(Discrete Cosine Transform)-transforming the image data is compressedinto a predetermined amount of data by a quantizer, the operation ofwhich is related to the following equations:

1) In intra mode:

QDC=dc/8

(i,j)=[16*ac(i,j)]//w(i,j)

QAC(i,j)=(i,j)//g

where g is a quantization step size and g=2*QUANT,W(i,j) is a weightmatrix, QAC is a quantized coefficient and QUANT is a quantizationlevel.

2) In non-intra mode: $\begin{matrix}{{{{QAC}\left( {i,j} \right)} = \quad {{{ac}\left( {i,j} \right)}/\left( {2*{QUANT}} \right)}},{{QUANT} = {odd}}} \\{{= \quad {\left\lbrack {{{ac}\left( {i,j} \right)} + 1} \right\rbrack/\left( {2*{QUANT}} \right)}},} \\{\quad {{{QUANT} = {even}},{{{ac}\left( {i,j} \right)} > 0}}} \\{{= \quad {\left\lbrack {{{ac}\left( {i,j} \right)} - 1} \right\rbrack/\left( {2*{QUANT}} \right)}},} \\{\quad {{{QUANT} = {even}},{{{ac}\left( {i,j} \right)} < 0}}}\end{matrix}$

In the above equations, the DCT coefficients may be divided into dccoefficients having concentrated energy and ac coefficients having alarge value of energy dispersion. Also, the quantizer performsquantization in two modes i.e., an intra mode and a non-intra mode. Thatis, the interrelationship of an input data is detected and if thedetected interrelationship is relatively low, the intra mode isperformed in which the dc and ac coefficients are quantized in differentmanners, while if the detected interrelationship is relatively high, thenon-intra mode is performed in which the quantization is performedaccording to the above equation regardless of the dc or ac coefficients.

Inverse quantization is the inverse process of quantization, by whichthe dc or ac coefficients are calculated in accordance with the valuesof the quantized coefficients QAC and the quantization level QUANT.

FIG. 1 shows the construction of a conventional decoder adopting theMPEG SM3 standard as described above. According to the decoder of FIG.1, data outputted from header detection section 1 for detecting a headersignal from an input data is inputted to VLC(Variable Length Code)decoder 3 through buffer 2.

VLC decoder 3 converts the input data into a FLC(Fixed Length Code) andthe FLC is then inverse-quantized by inverse quantizer 4. The output ofinverse quantizer 4 is inverse-DCT-transformed by inverse DCT section 5and the output of inverse DCT section 5 is applied to adder 7. At thistime, predictor 6 outputs a predicted value in accordance with theoutputs of VLC decoder 3 and adder 7, and this predicted value isapplied to adder 7 to be added to the output of inverse DCT section 5.Adder 7 outputs a final decoded signal.

The inverse quantizer mentioned as above, however, suffers fromdisadvantages in that hardware construction thereof is greatlycomplicated, causing the manufacturing cost to be increased and possiblycomplicating to a high degree the timing control for real time dataprocessing as well.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide an inversequantizing device which has a simple structure utilizing memories, andthereby great reductions in manufacturing costs can be achieved.

It is another object of the present invention to provide an inversequantizing device which enables real time processing of input data andeasy control therefor.

In order to achieve the above objects, the inverse quantizing deviceaccording to the present invention comprises:

a plurality of memories for receiving input quantized coefficients andquantization levels as their address data and storing resultant data ofinverse quantization in groups; and

control means for discriminating the group of the input data to beinverse-quantized in accordance with an input block-type andblock-strobe signals and providing a selection control signal forselecting one of said plurality of memories which stores the resultantdata of the discriminated group;

whereby the resultant data stored at an address of the selected memorywhich is assigned by the input quantized coefficients and thequantization levels is provided.

BRIEF DESCRIPTION OF THE DRAWINGS

The above objects and other features of the present invention willbecome more apparent by describing the preferred embodiment thereof withreference to the accompanying drawings, in which:

FIG. 1 is a schematic block diagram of a conventional decoder.

FIG. 2 is a schematic block diagram of the inverse quantizing deviceaccording to the present invention.

FIG. 3 is a circuit diagram of the control section in FIG. 2.

FIG. 4 is a truth table explaining the operation of the control sectionof FIG. 3.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 2 shows the construction of the inverse quantizing device accordingto the present invention. Referring to FIG. 2, the inverse quantizingdevice is provided with intra DC memory 42, intra AC memory 43 andnon-intra DC/AC memory 44 each of which receives quantized coefficientsQAC and quantization level values QUANT outputted from VLC decoder 3 astheir address data, stores the resultant data of inverse quantization ingroups, and outputs the resultant data to inverse DCT section 5.

The device is also provided with control section 41 which discriminateswhether the input data is an intra DC, an intra AC or a non-intra dataand selectively outputs first to third chip selection signals {overscore(IDCS)}, {overscore (IACS)} and {overscore (INS)}to chip selectionterminals {overscore (CS1)} to {overscore (CS3)} of the memories 42 to44 in accordance with the discriminated result.

In the embodiment, each memory 42, 43 or 44 is composed of aPROM(Programmable Road Only Memory).

Meanwhile, control section 41, as shown in FIG. 3, comprises first ORgate OR1 for OR-gating block-type signal {overscore (BKT)} andblock-strobe signal {overscore (BKS)} to output first chip selectionsignal {overscore (IDCS)}, second OR gate OR2 for OR-gating block-strobesignal {overscore (BKS)} inverted by first inverter IV1 and block-typesignal {overscore (BKT)} to output second chip selection signal{overscore (IACS)}, and second inverter IV2 for inverting block-typesignal {overscore (BKT)} and outputting the inverted block-type signal{overscore (BKT)} as third chip selection signal {overscore (NIS)}.

Now, the operation of the inverse quantizing device according to thepresent invention constructed as above will be described in detail.

Each R.G.B. signal, which constitutes a television signal, has agradation degree of a predetermined level, and thus the DCT-transformeddata of the gradation level and the quantized data of theDCT-transformed data have predetermined levels, respectively. Accordingto the present invention, all possible quantized level values are storedin the memories 42 to 44 so that one of the quantized level values isselected and outputted therefrom. Thus, real time data processing can beachieved.

Referring again to FIG. 2, DCT coefficient values QAC and quantizationlevel values QUANT provided from VLC decoder 3 are inputted to intra DCmemory 42, intra AC memory 43 and non-intra DC/AC memory 44,respectively, as their address data. Such address data may be expressedin terms of 64 samples since inverse quantization should be performedwith respect to 64 sample data in order to inverse-quantize an 8×8 IDCTdata block.

Also, as described above, the resultant data of vertical inversequantization are stored at addresses of the memories 42 to 44 inconformity with the group of the resultant data.

Meanwhile, the block-type signal {overscore (BKT)} identifying whetherthe input block data to be inverse-quantized is intra or non-intra, andblock-strobe signal {overscore (BKS)} identifying the start of the blockdata are also provided from VLC decoder 3 to control section 41.

At this time, as shown in the truth table of FIG. 4, if the input blockdata to be inverse-quantized is intra and the start of the block data isidentified, both of block-type signal {overscore (BKT)} and block-strobesignal {overscore (BKS)} become LOW(“0”), and as shown in FIG. 3, chipselection signal {overscore (IDCS)} of a LOW level is outputted from ORgate OR1 in control section 41 and then applied to chip selectionterminal {overscore (CS1)} of intra DC memory 42. Accordingly, intra DCmemory 42 is selected and the resultant data of inverse quantizationstored at its address assigned by the input QAC and QUANT is outputtedto inverse DCT section 5.

Also, if the input block data is intra and the middle or the end of theblock data is identified, block-type signal {overscore (BKT)} becomesLOW(“0”) and block-strobe signal {overscore (BKS)} becomes HIGH(“1”),and chip selection signal {overscore (IACS)} of a LOW level is outputtedfrom OR gate OR2 and then applied to chip selection terminal {overscore(CS2)} of intra AC memory 43. Accordingly, intra AC memory 43 isselected and the resultant data of inverse quantization stored at itsaddress assigned by QAC and QUANT is outputted to inverse DCT section 5.

Meanwhile, if the input block data is non-intra, block-type signal{overscore (BKT)} becomes HIGH(“1”) and thus both outputs of OR gatesOR1 and OR2 become HIGH regardless of the state of block-strobe signal{overscore (BKS)}. Accordingly, chip selection signal {overscore (NIS)}of a LOW level is outputted from inverter IV2 and then applied to chipselection terminal {overscore (CS3)} of non-intra DC/AC memory 44,resulting in that non-intra DC/AC memory 44 is selected and theresultant data of inverse quantization stored at its address assigned byQAC and QUANT is outputted to inverse DCT section 5.

From the foregoing, it will be apparent that the present inventionprovides a novel inverse quantizer specially designed to store in groupsall possible resultant data of inverse quantization in memories whichare addressed by the input quantized coefficients and quantizationlevels and provide the resultant data of inverse quantization stored inone of the memories in accordance with the input block-type andblock-strobe signals, thereby enabling real time processing of the inputdata and easy control of the data processing and achieving greatreductions in construction and cost.

While the present invention has been described and illustrated hereinwith reference to the preferred embodiment thereof, it will beunderstood by those skilled in the art that various changes in form anddetails may be made therein without departing from the spirit and scopeof the invention.

What is claimed is:
 1. An inverse quantizing device comprising: aplurality of memories for receiving input quantized coefficients andquantization levels as address data thereof and storing resultant dataof inverse quantization in groups; and control means for discriminatingthe group of an input data to be inverse-quantized in accordance withinput block-type and block-strobe signals and providing a selectioncontrol signal for selecting one of said plurality of memories storingsaid resultant data of the discriminated group; whereby said resultantdata stored at the address of the selected one of said plurality ofmemories assigned by said quantized coefficients and said quantizationlevels is provided, wherein said resultant data of inverse quantizationare grouped into block data of intra DC, intra AC and non-intra,respectively, and said plurality of memories are an intra DC memory, anintra AC memory and a non-intra DC/AC memory.
 2. An inverse quantizingdevice comprising: a plurality of memories for receiving input quantizedcoefficients and quantization levels as address data thereof and storingresultant data of inverse quantization in groups; and control means fordiscriminating the group of an input data to be inverse-quantized inaccordance with input block-type and block-strobe signals and providinga selection control signal for selecting one of said plurality ofmemories storing said resultant data of the discriminated group; wherebysaid resultant data stored at the address of the selected one of saidplurality of memories assigned by said quantized coefficients and saidquantization levels is provided, wherein said plurality of memories areprogrammable read only memories.
 3. An inverse quantizing devicecomprising: a plurality of memories for receiving input quantizedcoefficients and quantization levels as address data thereof and storingresultant data of inverse quantization in groups; and control means fordiscriminating the group of an input data to be inverse-quantized inaccordance with input block-type and block-strobe signals and providinga selection control signal for selecting one of said plurality ofmemories storing said resultant data of the discriminated group; wherebysaid resultant data stored at the address of the selected one of saidplurality of memories assigned by said quantized coefficients and saidquantization levels is provided, wherein said control means comprises: afirst OR gate for OR-gating said block-type and block-strobe signals andproviding a first chip selection signal; a first inverter for invertingsaid block-strobe signal; a second OR gate for OR-gating the invertedblock-strobe signal and said block-type signal and providing a secondchip selection signal; and a second inverter for inverting saidblock-type signal and providing a third chip selection signal.
 4. Aninverse quantization device for a decoder, comprising: a storage devicethat stores a plurality of quantized level values, said storage devicestores ( 1 ) a corresponding resultant data of the inverse quantizationwhen an input data is a first mode type data or stores ( 2 ) acorresponding resultant data of the inverse quantization when the inputdata is a second mode type data; and a control device discriminating theinput data to be inverse-quantized according to the mode type data andcontrolling the storage device to determine the resultant data to bestored according to the discriminated result.
 5. The inversequantization device of claim 4, wherein the first and second mode typedata comprise intra mode and non-intra mode data, respectively.
 6. Theinverse quantization device of claim 4, wherein said storage devicestores a corresponding resultant data of the inverse quantization whenthe input data is a third mode type data.
 7. The inverse quantizationdevice of claim 6, wherein said input data comprises quantizedcoefficients and quantization levels.
 8. The inverse quantization deviceof claim 6, wherein the first, second, and third mode type data compriseintra DC mode, non-intra mode and intra AC mode data, respectively. 9.The inverse quantization device of claim 6, wherein said storage devicecomprises: a first memory storing resultant data of the inversequantization corresponding to the first mode type data and responsive tothe control device; a second memory storing resultant data of theinverse quantization corresponding to the second mode type data andresponsive to the control device; and a third memory storing resultantdata of the inverse quantization corresponding to the third mode typedata and responsive to the control device.
 10. The inverse quantizationdevice of claim 9, wherein each of said first, second and third memoriescomprises a programmable read only memory.
 11. The inverse quantizationdevice of claim 4, wherein said storage device stores all resultant dataof the inverse quantization.
 12. The inverse quantization device ofclaim 6, wherein said control device comprises: a first logic devicehaving first and second input electrodes and performing a first logicoperation; a second logic device having first and second inputelectrodes and performing a second logic operation; and a firstinverter, wherein wherein said first logic device, said second logicdevice and said first inverter discriminate the input data to beinverse-quantized according to the mode type data.
 13. The inversequantization device of claim 12 further comprising a second invertercoupled to the first input electrodes of said second logic device. 14.The inverse quantization device of claim 13, wherein said first andsecond logic devices are OR gates.
 15. An inverse quantization devicefor a decoder, comprising: a storage device that stores a plurality ofquantized level values and receiving input data of at least one ofquantized coefficient and quantization level as an address location forselecting a stored quantized level value; and a control circuit,responsive to first and second control signals indicative of whether theinput data is one of intra DC data, intra AC data and non-intra data,for outputting first, second and third output signals to said storagedevice, wherein said storage device stores one of ( 1 ) a resultant dataof the inverse quantization corresponding to intra DC data in responseto the first output signal, ( 2 ) a resultant data of the inversequantization corresponding to intra AC data in response to the secondoutput signal, and ( 3 ) a resultant data of the inverse quantizationcorresponding to non-intra data in response to the third output signal.16. The inverse quantization device of claim 15, wherein said storagedevice is a programmable read only memory.
 17. The inverse quantizationdevice of claim 15, wherein said storage device comprises: a firstmemory that stores the resultant data of the inverse quantizationcorresponding to intra DC data; a second memory that stores theresultant data of the inverse quantization corresponding to intra ACdata; and a third memory that stores the resultant data of the inversequantization corresponding to non-intra data.
 18. The inversequantization device of claim 15, wherein said control circuit comprises:a first logic device having first and second input electrodes andperforming a first logic operation to provide the first output signal; asecond logic device having first and second input electrodes andperforming a second logic operation to provide the second output signal;and a first inverter for providing the third output signal, wherein thefirst input electrodes of said first and second logic devices arecoupled for receiving the second control signal, and the second inputelectrodes of the first and second logic devices and the first inverterare coupled for receiving the first control signal.
 19. The inversequantization device of claim 18 further comprising a second invertercoupled to the first input electrodes of said second logic device forproviding an inverted second control signal to said second logic gate.20. The inverse quantization device of claim 19, wherein said first andsecond logic devices are OR gates.